The present invention is directed generally to a semiconductor method of manufacture, and more particularly to such a method involving plasma etching in the formation of electrodes, such as gate electrodes.
The electronics industry continues to strive for high-speed, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. The main objective in manufacturing such devices is to obtain a device which conforms to geographical features of a particular design for the device. To obtain this objective, steps in the manufacturing process are closely-controlled to ensure that rigid requirements, for example, exacting tolerances, quality materials, and clean environment, are realized.
Semiconductor devices are used in large numbers to construct most modern electronic devices. To increase the capability of such electronic devices or to decrease the costs per die in a competitive market, larger numbers of such devices are integrated into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) to address these needs, the structure of the devices and fabrication techniques used to make such devices must be refined to remove contaminants and tighten tolerances on acceptable structural imperfections.
A wide variety of processing techniques may be employed in manufacturing silicon integrated circuit devices, such as chips. In those devices, silicon is employed as a semiconductor for conduction of electricity. The chip manufacturing process typically begins with a silicon wafer substrate. The silicon wafer substrate is formed of single-crystal silicon (Si).
Typical steps in the manufacturing process of a silicon integrated circuit device include growing a layer of silicon dioxide (SiO2, or xe2x80x9coxidexe2x80x9d) upon the surface of the wafer. Silicon dioxide (or other dielectrics) serves as an insulative material and is often used to separate various semiconducting layers of integrated circuit devices. A variety of methods may be employed to force oxide growth on the wafer, including, for example, thermal oxidation. In thermal oxidation, the silicon reacts with oxygen to form a continuous layer of high-quality silicon dioxide. A film of silicon dioxide can also be formed on the surface of a wafer in other manners. Amorphous or polycrystalline silicon is then deposited on the oxide. For simplicity, these films will be referred to as xe2x80x9cpolysiliconxe2x80x9d here. An organic or inorganic anti-reflective coating (ARC) film may be deposited on top of the polysilicon to improve control of the photolithography process. A variety of techniques, including, for example, photolithography, may be employed to achieve desired wafer surface configurations.
In photolithography, a photoresist material, for example, a photo-sensitive polymer, may be layered atop a somewhat uniform polysilicon or ARC layer on a wafer surface. A mask having a desired design of clear and opaque areas may then be positioned atop the photoresist layer. A resulting characteristic of photoresist response to UV light permits the photoresist to be selectively subjected to UV light and then developed to leave behind an image that will serve as a mask for forming particular patterns of photoresist material atop the polysilicon or ARC. Once a particular pattern of photoresist is formed atop the polysilicon or ARC of a wafer, portions of the wafer topped by polysilicon or ARC but not topped by photoresist may then be etched away from the wafer surface.
Etching is a common procedure employed in manufacture of silicon integrated circuit devices. In general terms, etching is a process by which portions of the wafer surface may be selectively removed from the wafer. The etch process yields a layer on the wafer surface having a desired geographical arrangement for further processing. After the etch, the photoresist is removed by a subsequent processing step, leaving the silicon wafer topped only by select configurations of polysilicon or ARC.
The general silicon dioxide/polysilicon/ARC/photoresist/etch method described above is often used in the formation of the gate electrode portion of a transistor. Such gate electrode formation involves layering an oxide, followed by a conductive polysilicon layer, over the underlying (typically doped) silicon used to form the active and isolation regions. The portions of the conductive polysilicon layer designated to form the resultant gate electrodes are hardmasked, for example, using SiON. Gate electrodes are then formed by selectively etching the conductive polysilicon in such a manner that trenches are formed between adjacent gate electrodes. Selectively etching in this context refers to etching the unmasked material, thereby providing a trench with substantially vertical sidewalls.
The ideal selective etching process would provide perfectly vertical sidewalls that provide an interface at the trench bottom which is normal. In practice, however, process changes made to increase silicon-to-oxide selectivity result in notching at the bottom of the gate electrode. FIG. 1 illustrates this notching effect at the bottom of the pillar-like electrode structures.
In modern semiconductor applications, the thickness of the underlying layer of gate oxide has been reduced to about 30 xc3x85 for 0.15 micron and similar technologies. In the future, the gate oxide layer will be thinned further, perhaps to as little as 15-20 xc3x85. Due to the notching problem described above, the plasma etch process conventionally used to define the gate electrode inevitably consumes some of this oxide; consequently, process changes are made to boost silicon-to-oxide selectivity to minimize the loss. In the prior art, changes such as reducing bias power have been found to be useful for improving selectivity, but with the disadvantage of lateral etching beginning to occur as the sidewall protection of the gate electrode is diminished. This lateral etching typically appears as a notch at the gate/oxide interface.
Accordingly, there is a need to improve the process of forming the gate electrode in a manner that overcomes the aforementioned deficiencies.
Generally, the present invention relates to a semiconductor device manufactured using a more accurate gate-electrode formation process. Consistent with the present invention, a semiconductor device is formed as part of a wafer having an upper surface, with at least one device layer over the upper surface of the wafer. The device layer is formed using a silicon-to-oxide selectivity during gate etch to improve sidewall protection and to eliminate notching at the bottom of the gate electrode. In connection with the one embodiment of the present invention, it has been discovered that adding a small amount of nitrogen during the endpoint step prevents the notch without affecting selectivity. A more specific embodiment of the present invention provides a method for improving sidewall protection and preventing notch formation without affecting silicon:oxide selectivity. During the endpoint step, a small amount of nitrogen is added to the conventional polysilicon etch chemistry.
In accordance with another embodiment of the present invention, a process of forming a semiconductor device, includes: forming at least one device layer over a wafer surface; providing a mask over a portion of the device layer; using a plasma-etch and selective etching into the device layer to form a pillar structure having at least one sidewall, the selective etching includes the use of nitrogen as part of the plasma etch.
Yet another embodiment of the present invention is directed to a process of forming a semiconductor device, comprising: forming at least one device layer over an underlying dielectric layer, the device layer and the underlying dielectric layer being over a wafer surface, providing a mask over a portion of the device layer; a step of using a plasma-etch of a first chemistry and selectively etching into the device layer for a function of forming a pillar structure having at least one sidewall. After the step of using the first chemistry, using a step of using a plasma-etch of a different second chemistry that includes less than about ten percent nitrogen of gas flow in the second chemistry for a function of completing the selective etching upon etching up to the underlying dielectric layer. In another embodiment, the second chemistry includes less than about five percent of the gas flow.
In another embodiment, a process of forming a semiconductor device includes forming at least one gate electrode layer over a gate oxide; providing a hardmask over a portion of the device layer; using a plasma-etch of a first chemistry that includes HBr and selectively etching into the device layer to form a pillar structure having at least one sidewall. After using the first chemistry, a plasma-etch of a different second chemistry that includes HBr and nitrogen and selectively etching into the device layer to form a pillar structure having at least one sidewall is used. The second chemistry includes using nitrogen in an amount less than about ten percent of gas flow of the second chemistry and terminating the use of a plasma-etch of the second chemistry in response to reaching the gate oxide. The first chemistry can include HBr/Cl2, HBr/HCl, or HBr/Cl2/Cl4 for etching through the polysilicon, and can also include a selectivity booster such as Hexe2x80x94O2.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.